Input Data Port Dma Control Registers; Idp_Dma_Ix - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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Input Data Port Registers

Table A-18. IDP_FIFO Register Bit Descriptions

Input Data Port DMA Control Registers

Each of the eight DMA channels have an I-register with an index pointer

(19 bits), an M-register with a modifier/stride (6 bits), and a C-register

with a count (16 bits). For example,

control the DMA for IDP channel 0. The following sections

describe these registers.

provides information about the IDP DMA index registers.

Table A-19. IDP_DMA_Ix Registers

IDP Channel Encoding. These bits indicate the serial input port

channel number that provided this serial input data.

Note: This information is not valid when data comes from the PDAP.

Left/Right Channel Status. Indicates whether the data in bits 31-4 is

the left or the right audio channel as dictated by the frame sync sig-

nal. The polarity of the encoding depends on the serial mode selected

in IDP_SMODE for that channel. See

Input Data (Serial). Some LSBs can be zero, depending on the mode.

ADSP-21368 SHARC Processor Hardware Reference

Table A-16 on page

IDP channel 0 DMA index register

IDP channel 1 DMA index register

IDP channel 2 DMA index register

IDP channel 3 DMA index register

IDP channel 4 DMA index register

IDP channel 5 DMA index register