Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 821

Table A-70. PMCTL Register Bit Descriptions (Cont'd)
Bit Name
14 UART1OFF
15 PLLBP
16 CRAT0
17 CRAT1
20–18 SDCKR
21 TWIOFF
22 SDRAMOFF
23 PWMOFF
24 DTCPOFF
ADSP-21368 SHARC Processor Hardware Reference
Description
UART1 Clock Enable.
0 = UART1 is in normal mode
1 = Shut down clock to UART1
PLL Bypass Mode Indication.
0 = PLL is in normal mode
1 = Put PLL in bypass mode
Reset value = 0
PLL Clock Ratio, CLKIN to CK (read only). Read only. For
more detail, see the PLLM and PLLDx bit descriptions in this
table.
Reset value = CLK_CFG[1:0]
PLL Clock Ratio, CLKIN to CK (read only). For more
detail, see the PLLM and PLLDx bit descriptions in this table.
Reset value = CLK_CFG[1:0]
SDCLK Ratio. Core clock to SDRAM clock.
000 = RATIO = 2
001 = RATIO = 2.5
010 = RATIO = 3.0
011 = RATIO = 3.5
100 = RATIO = 4.0
101, 110, 111 = Reserved
TWI Clock Enable.
0 = TWI is in normal mode
1 = Shut down clock to TWI
SDRAM Clock Enable.
0 = SDRAM is in normal mode
1 = Shut down clock to SDRAM
PWM Clock Enable.
0 = PWM is in normal mode
1 = Shut down clock to PWM
DTCP Clock Enable.
0 = DTCP is in normal mode
1 = Shut down clock to DTCP
Register Reference
A-173