Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 441

Starting Ping-Pong DMA Transfers
To start a ping-pong DMA transfer from the FIFO to memory:
1. Clear and halt the FIFO by setting (= 1) and then clearing (= 0) the
IDP_ENABLE
2. While the
for the following DMA parameter registers that correspond to
channels 7–0. If some channels are not going to be used, then the
corresponding parameter registers can be left in their default states:
• First index registers
• Second index registers
• Modifier register
• Counter register
is 0–7 which corresponds to channels 0 to 7. See
Ping-Pong Count Registers (IDP_DMA_PCx)" on
page
3. Keep the clock and the frame sync input of the serial inputs and/or
the PDAP connected to low, by setting proper values in the
SRU_CLK2
ters. For more information, see "DAI/SRU1 Connection Groups"
on page 4-18.
4. Set the required values for:
•
IDP_SMODEx
sync format for the serial inputs (I
pair, or right-justified sample pair modes).
ADSP-21368 SHARC Processor Hardware Reference
bit (bit 7 in the
and
IDP_DMA_EN IDP_ENABLE
IDP_DMA_AIx
IDP_DMA_Mx
IDP_DMA_PCx
A-73.
and as well as the
SRU_CLK3
bits in the
register).
IDP_CTL0
bits are low, set the values
IDP_DMA_BIx
. For each of these registers x
SRU_FS2
register to specify the frame
IDP_CTL0
2
S, left-justified sample
Input Data Port
"IDP
and regis-
SRU_FS3
7-23