16-Bit Receive Fifo Register; Data Transfer Mechanics - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Data Transfer Mechanics

16-Bit Receive FIFO Register

The TWI 16- bit FIFO receive register (
read from the FIFO buffer. Although peripheral bus reads are 32 bits, a
read access to the
from the FIFO buffer. To reduce interrupt output rates and peripheral
bus access times, a double-byte receive data access can be performed. Two
data bytes can be read, effectively emptying the receive FIFO buffer with a
single access.
The data is read in little-endian byte order, as shown in
page 12-9, where byte 0 is the first byte received and byte 1 is the second
byte received. With each access, the receive status (
register is updated to indicate it is empty. If an access is per-
TWIFIFOSTAT
formed while the FIFO buffer is not full, the core waits until the receive
FIFO buffer is full and then completes the read access. All bits in this reg-
ister are write-only.
Register (RXTWI16)" on page A-154.
Data Transfer Mechanics
The TWI controller follows the transfer protocol of the Philips I
Specification version 2.1 dated January 2000. A simple complete transfer is
diagrammed in
S
S = START
P = STOP
ACK = ACKNOWLEDGE
Figure 12-3. Basic Data Transfer
12-10
register can only access two receive data bytes
RXTWI16
For more information, see "16-Bit Receive FIFO
Figure 12-3.
7-BIT ADDRESS R/W
ADSP-21368 SHARC Processor Hardware Reference
) holds a 16-bit data value
RXTWI16
TWIRXS
ACK 8-BIT DATA
Figure 12-2 on
) field in the
2
C Bus
ACK P