Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 710

Serial Peripheral Interface Registers
SPI DMA Configuration Registers (SPIDMAC, SPIDMACB)
These registers addresses are 0x1084 (for
) and their reset value is undefined. These 17-bit SPI registers, shown
MACB
in Figure A-26
transfers.
SPIDMAC (0x1084)
SPIDMACB (0x2884)
Reserved
SPIDMAS
DMA Transfer Status
1=DMA transfer in progress
0=DMA Idle
SPIERRS
DMA Error Status
1=Error during transfer
0=Successful DMA transfer
SPISx
DMA FIFO Status
00=FIFO empty, 11=FIFO full,
10=FIFO partially full
SPIMME
Multimaster Error
1=Error during transfer
0=Successful transfer
SPIUNF
Transmit Underflow Error (SPIRCV=1)
1=Transmission error occurred with transmit
buffer empty
0=Successful transfer
SPIOVF
Receive Overflow Error (SPIRCV=1)
1=Error: data received with receive buffer full
0=Successful transfer
Figure A-26. SPIDMAC, SPIDMACB Registers
A-62
and described in Table
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9
0 0 0 0 0 0 0
ADSP-21368 SHARC Processor Hardware Reference
) and 0x2884 (for
SPIDMAC
A-15, are used to control DMA
0 0 0 0 0 0 0
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
SPID-
0
SPICHS
DMA Chain Loading Status
1=DMA chain pointer loading
in progress
0=DMA chain idle
0
0
SPIDEN
DMA Enable
1=DMA enabled
0=DMA disabled
SPIRCV
DMA Write/Read
1=Memory read (SPI transmit)
0=Memory write (SPI receive)
INTEN
Enable DMA Interrupt on
Transfer
1=Enable
0=Disable
Reserved
SPICHEN
SPI DMA Chaining Enable
1=Enable
0=Disable
Reserved
FIFOFLSH
DMA FIFO Clear
1=Enable
0=Disable
INTERR
Enable Interrupt on Error
1=Enable
0=Disable