Interrupt Enable Register; 16-Bit Transmit Fifo Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Register Descriptions
After servicing the interrupt source associated with a bit, programs must
clear that interrupt source bit. All bits are sticky and W1C-type.
information, see "Interrupt Source Register (TWIIRPTL)" on
page A-147.

Interrupt Enable Register

The TWI interrupt enable register (
assert the interrupt output. Each enable bit corresponds with one inter-
rupt source bit in the TWI interrupt source register (
and writing the TWI interrupt enable register does not affect the contents
of the TWI interrupt source register. For all bits, 0 = interrupt generation
disabled and 1 = interrupt generation enabled.
"Interrupt Enable Register (TWIIMASK)" on page A-150.
8-Bit Transmit FIFO Register
The TWI 8-bit transmit FIFO register (
written into the FIFO buffer. Transmit data is entered into the corre-
sponding transmit buffer in a first-in, first-out order. Although peripheral
bus writes are 32 bits, a write access to the
transmit data byte to the FIFO buffer. With each access, the transmit sta-
tus ( ) field in the
TWITXS
performed while the FIFO buffer is full, the core waits until there is at
least one byte space in the transmit FIFO buffer and then completes the
write access. The bits in this register are write-only.
see "8-Bit Transmit FIFO Register (TXTWI8)" on page A-152.

16-Bit Transmit FIFO Register

The TWI 16-bit FIFO transmit register (
value written into the FIFO buffer. Although peripheral bus writes are 32
bits, a write access to the
bytes to the FIFO buffer. To reduce interrupt output rates and peripheral
12-8
TWIIMASK
register is updated. If an access is
TWIFIFOSTAT
register adds only two transmit data
TXTWI16
ADSP-21368 SHARC Processor Hardware Reference
) allows interrupt sources to
TWIIRPTL
For more information, see
) holds an 8-bit data value
TXTWI8
register adds only one
TXTWI8
For more information,
) holds a 16-bit data
TXTWI16
For more
). Reading