Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 314

SPORT Operation Modes
Programming Packed I
Since packed I
this modes is the same as programming TDM. Use the serial port control
( ) and channel selection registers to configure the serial ports to run
SPCTLx
2
in packed I S mode as follows.
1. Set the
the processor to run in packed I
2. Configure the
master or slave which in this case is internal or external clock and
frame sync.
In the I
and the slave uses external clock and frame sync.
3. Configure the channel select registers. See
isters" on page
4. Set the
emulate I
In the I
ing edge and the receiver samples the input at the clock rising edge.
This does not apply to packed I
5. Clear (= 0) the
2
I S mode. In the I
packed I
6. To emulate I
SPMCTLx
the first bit of data immediately upon the frame sync pulsing high.
In the I
frame sync pulse toggles.
5-34
2
S Mode
2
S mode is implemented on top of TDM, programming
bit (bit 11, = 1) in the
OPMODE
(bit 10) and
ICLK
2
S standard, the master generates both clock and frame sync
5-31.
bit (bit 12) to 1 in both transmitter and receiver to
CKRE
2
S mode.
2
S standard, the transmitter drives output at the clock fall-
bit in both transmitter and receiver to emulate
LSBF
2
S standard, the MSB of a word is sent first. In
2
S mode, this is not the case.
2
S in packed I
register. In TDM mode, the transmitter starts to transmit
2
S standard, data transmission starts one cycle after the
ADSP-21368 SHARC Processor Hardware Reference
SPCTLx
2
S mode.
(bit 14) bits to emulate I
IFS
"Channel Selection Reg-
2
S mode.
2
S mode, set (=1) the
register to configure
2
S
bit in the
MFD