Pulse Width Modulation Registers - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Pulse Width Modulation Registers

Table A-24. IDP_PP_CTL Register Bit Descriptions (Cont'd)
Bit Name
30 IDP_PDAP_RESET
31 IDP_PDAP_EN
Pulse Width Modulation Registers
The following registers control the operation of pulse width modulation
on the ADSP-21367/8/9 and ADSP-2137x processors.
PWM Global Control Register (PWMGCTL)
Use this register, shown in
PWM groups in any combination. This provides synchronization across
the groups. This 16-bit, read/write register is located at address 0x3800.
A-78
Description
PDAP Reset. Setting this bit (=1) causes the PDAP
reset circuit to strobe, then this bit is cleared auto-
matically.
This bit always returns a value of zero when read.
PDAP Enable.
0 = Disables the 20 DAI pins or the DATA31–8 pins
from use as parallel input channels.
1 = Enables either the 20 DAI pins or the
DATA31–8 pins to be used as a parallel input chan-
nel. IDP channel 0 cannot be used as a serial input
port with this setting.
Figure A-31, to enable or disable the four
ADSP-21368 SHARC Processor Hardware Reference