Multichannel Mode Control Bits - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

After the
TXSPxA
signal is generated. When SPORT DMA is used, this signal
SPORTx_TDV
may occur several cycles after the multichannel transmission is enabled. If
a deterministic start time is required, pre-load the transmit buffer.
Active State Multichannel Frame Sync Select
The bit in the
LFS
nel frame sync signals as active low (inverted) if set (=1), or active high if
cleared (=0). Active high (=0) is the default.

Multichannel Mode Control Bits

Several bits in the
nel mode operation:
• Operation mode (
• Word length (
• SPORT transmit/receive enable (
• Master mode enable (
If the
MCEA
SPEN_A
The control registers contain several bits that enable and configure
SPCTLx
multichannel operations. Refer to
Multichannel mode is enabled by setting the
through
SPMCTL0
• When the
enabled.
• When the
ations are disabled.
ADSP-21368 SHARC Processor Hardware Reference
transmit buffer is loaded, transmission begins and the
, registers selects the logic level of the multichan-
SPCTLx
control register enable and configure multichan-
SPCTLx
)
OPMODE
)
SLEN
MSTR
or bits are set (=1) in the
MCEB
and bits in the
SPEN_B
control register:
SPMCTL7
or bits are set (=1), multichannel operation is
MCEA MCEB
or bits are cleared (=0), all multichannel oper-
MCEA MCEB
and
SDEN_A
)
SPMCTLx
register must be cleared (=0).
SPCTL
Table 5-9 on page
or
MCEA
Serial Ports
)
SDEN_B
register, the
5-59.
bit in the
MCEB
5-29