Dma Stalls; Iop Buffer Stalls - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Data Delays, Latencies, and Throughput

DMA Stalls

• One cycle if an access to a DMA parameter register conflicts with
the DMA address generation (for example, writing to the register
while a register update is taking place) or reading while a DMA
register conflicts with DMA chaining.
• Attempting to write to (or read from) a full (or empty) DMA
buffer causes the core to hang indefinitely, unless the
hang disable) bit for that peripheral is set (for example in the corre-
sponding

IOP Buffer Stalls

Table 14-16 shows the number of stalls incurred with the I/O processor
when writing to a full buffer or reading from an empty buffer.
Table 14-16. Latencies and Throughput
Operation
Interrupts (IRQ2-0)
DMA chain initialization
1
Serial ports
1 ADSP-2136x SHARC processor-to-ADSP-2136x SHARC processor transfers using 32-bit
words.
14-56
register for a serial port).
SPCTLx
ADSP-21368 SHARC Processor Hardware Reference
BHD
Minimum Data Maximum
Delay (cycles) Throughput
(cycles/ transfer)
3 -
7–11 -
35 32
(buffer