S/Pdif Transmitter - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

A set of three preambles, shown in
are transmitted in the time allocated to four time slots at the start of each
subframe (time slots 0 to 3) and are represented by eight successive states.
The first state of the preamble is always different from the second state of
the previous symbol (representing the parity bit).
Table 9-1. Preambles
Preamble
X
Y
Z
Like bi-phase code, the preambles are dc free and provide clock recovery.
They differ in at least two states from any valid bi-phase sequence.

S/PDIF Transmitter

The S/PDIF transmitter resides within the DAI, and its inputs and out-
puts can be routed through the signal routing unit (SRU1). It receives
audio data in serial format, encloses the specified user status information,
and converts it into the bi-phase encoded signal. The serial data input to
the transmitter can be formatted as left-justified, I
with word widths of 16, 18, 20 or 24 bits.
The serial data, clock, external sync signal, and frame sync inputs to the
S/PDIF transmitter are routed through SRU1. They can come from a
variety of sources such as the SPORTs, external pins, the precision clock
generators (PCG), or the sample rate converters (SRC). The signal routing
is selected in the SRU1 control registers.
"DAI/SRU1 Connection Groups" on page
ADSP-21368 SHARC Processor Hardware Reference
Preceding state 0 Preceding state 1
11100010 00011101
11100100 00011011
11101000 00010111
S/PDIF Transmitter/Receiver
Table 9-1, are used. These preambles
Description
Subframe 1
Subframe 2
Subframe 1 and
block start
2
S, or right-justified
For more information, see
4-18.
9-7