System Status Register (Systat - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

System Status Register (SYSTAT)

The register's address is 0x180F. The reset value has all bits initial-
SYSTAT
ized to zero, except for the
values on the ADSP-21367/8/9 and ADSP-2137x's pins. This register is
shown in Figure A-3
SYSTAT(0x180F)
Reserved
Reserved
IDC
ID Code. State of ID2–0 pins
Reserved
Figure A-3. SYSTAT Register
Table A-2. System Status Register (SYSTAT) Bit Descriptions
Bit Name
0 BSYN
3–1 Reserved (reset value =0)
6-4 CRBM
ADSP-21368 SHARC Processor Hardware Reference
,
IDC CRBM
and described in
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0
Description
Bus Synchronized. Indicates whether the processor's bus arbitration
logic is synchronized (if set, =1) or is not synchronized (if cleared,
=0, reset value).
Current Bus Master. These bits indicate the ID of the processor
that currently is the bus master in a multiprocessor system. Because
CRBM is only valid for DSPs with ID inputs other than zero (for
example, a multiprocessor system), the processor keeps CRBM set
to 001 when ID equals 000. The reset value of CRBM is undefined.
Register Reference
, and fields, which are set from
CRAT
Table A-2.
0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
0
0
0
BSYN
Bus Synchronized
1=Bus arbitration synchronized
0=Not synchronized
Reserved
CRBM
Current Bus Master
Status of ID of processor that is
current bus master
A-9