Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 342

SPORT Control Registers and Data Buffers
This description applies only to DSP standard serial and multichannel
modes only.
Serial word endian select.
little endian words (LSB first, if set, = 1) or big endian words (MSB first,
if cleared, = 0). This description applies to DSP standard serial and multi-
channel modes only.
Serial word length select.
select the word length in bits. Word sizes can be from 3 bits (
32 bits ( = 31). This bit applies to all operation modes.
SLEN
Use this formula to calculate the value for
= actual serial word length – 1
SLEN
The
SLEN
word length is limited to 8-32 bits. DSP standard mode word
length varies from 3-32 bits.
16-bit to 32-bit word packing enable.
bit enables (if set, = 1) or disables (if cleared, = 0) 16- to 32-bit word pack-
ing. This bit applies to all operation modes.
Internal clock select.
internal (if set, = 1) or external (if cleared, = 0) transmit or receive clock.
This bit applies to DSP standard serial mode and multichannel modes.
Sport operation mode.
2
I S, left-justified sample pair, and packed I
(= 1), or disables if cleared (= 0). This bit applies to all operation modes.
See Table 5-1 on page 5-11
page 5-12.
Clock rising edge select.
whether the SPORT uses the rising edge (if set, = 1) or falling edge (if
cleared, = 0) of the clock signal for sampling data and the frame sync. This
bit applies to DSP standard serial and multichannel modes only.
5-62
registers, bit 3 (
SPCTLx
registers, bits 8–4 (
SPCTLx
bit cannot equal 0 or 1. I
registers, bit 10 (
SPCTLx
registers, bit 11 (
SPCTLx
and "Standard DSP Serial Mode" on
registers, bit 12 (
SPCTLx
ADSP-21368 SHARC Processor Hardware Reference
). This bit selects
LSBF
SLENx
:
SLEN
2
S, and left-justified sample pair
registers, bit 9 (
SPCTLx
). This bit selects the
ICLK
). This bit enables
OPMODE
2
S in multichannel modes if set
). This bit selects
CKRE
). These bits
= 2) to
SLEN
). This
PACK