Hardware Breakpoint Control Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Hardware Breakpoint Control Register

The register controls how breakpoints are used if bit 25,
BRKCTL
set. This user-accessible register, shown in
and described in
The register is a 32-bit, memory-mapped I/O register. The core can write
into this register. The bits related to the register are the same as in the
"Enhanced Emulation Status Register" on page
Note that instruction address breakpoint negates such as
and
NEGDA1
BRKCTL (Bits 31-16)
Reserved
ENBIOY
Enable IOY Breakpoint
ENBIOX
Enable IOX Breakpoint
UMODE
Enable User Mode Breakpoint
1=Enable breakpoint
0=Disable breakpoint
ANDBKP
AND composite breakpoints
1=AND breakpoint types
0=OR breakpoint types
ENBEP
Enable External Port Address Break-
point (See ENBPA Bit Description)
Reserved
ENBIA
Enable Instruction Address Break-
points (See ENBPA Bit Description)
Figure A-84. BRKCTL Register (Bits 16–31)
ADSP-21368 SHARC Processor Hardware Reference
Table A-71, is located at address 0x30025.
have an effect latency of four core clock cycles.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Register Reference
Figure A-84
A-179.
0 0 0 0 0 0 0 0
, is
UMODE
and Figure A-85
NEGPA1
NEGIA4
Negate Instruction Address
Breakpoint #4
1=Enable breakpoint
0=Disable breakpoint
NEGIO1
Negate I/O Address
Breakpoint #1
1=Enable breakpoint
0=Disable breakpoint
NEGEP1
Negate External Address
Breakpoint #1
1=Enable breakpoint
0=Disable breakpoint
ENBPA
Enable Program Memory
Address Breakpoints
1=Enable breakpoint
0=Disable breakpoint
ENBDA
Enable Data Memory
Breakpoints
1=Enable breakpoint
0=Disable breakpoint
A-175