Listing 6-1. SPI Master Mode Core-Driven Transmit
/* SPI Control Registers */
#define SPICTL
#define SPIFLG
#define SPIBAUD (0x1005)
#define TXSPI
/*SPICTL bits*/
#define TIMOD1
#define DMISO
#define WL32
#define SPIMS
#define SPIEN
/*SPIFLG bits */
#define DS0EN
/* Default Buffer Length */
#define BUFSIZE 10
.SECTION/DM seg_dmda;
/* Transmit Buffer */
.var tx_buf[BUFSIZE] =
ADSP-21368 SHARC Processor Hardware Reference
Serial Peripheral Interface Ports
(0x1000)
(0x1001)
(0x1003)
(0x0001)
/* Use TX buffer for transfers */
(0x0020)
/* Disable MISO pin */
(0x0100)
/* SPI Word Length = 32 */
(0x1000)
/* SPI Master if 1, Slave if 0 */
(0x4000)
/* SPI port Enable */
(0x0001)
/* use FLG0 as SPI device-select*/
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xAAAAAAAA;
6-39
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