Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 811

Table A-68. PCG_SYNC2 Register Bit Descriptions (Cont'd)
Bit Name
3 FSC_SOURCE_IOP
16 FSD_SYNC
17 CLKD_SYNC
18 CLKD_SOURCE_IOP
19 FSD_SOURCE_IOP
ADSP-21368 SHARC Processor Hardware Reference
Description
Enable frame sync C input source.
0 = XTAL buffer output selected for frame sync C
1 = EXT_CLKA_I selected for frame sync C
Enable synchronization of frame sync D with external
frame sync.
0 = Frame sync disabled
1 = Frame sync enabled
Enable synchronization of clock D with external frame
sync.
0 = Clock disabled
1 = Clock enabled
Enable clock D input source.
0 = XTAL buffer output selected for clock D
1 = EXT_CLKA_I selected for clock D
Enable frame sync D input source.
0 = XTAL buffer output selected for frame sync D
1 = EXT_CLKA_I selected for frame sync D
Register Reference
A-163