Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 736

Sony/Philips Digital Interface Registers
Table A-33. DITCTL Register Bit Descriptions (Cont'd)
Bit Name
3–2 DIT_FREQ
4 DIT_SCDF
5 DIT_SCDF_LR
8–6 DIT_SMODEIN
9 DIT_
STANDALONE_
MODE
10 DIT_VALIDL
11 DIT_VALIDR
12 DIT_BLK_STAT
A-88
Description
Frequency Multiplier. Sets the oversampling ratio to the fol-
lowing:
00 = 256 x Frame sync
01 = 384 x Frame sync
10 = 512 x Frame sync
11 = 768 x Frame sync
Transmit Single-Channel, Double-Frequency Enable.
Select single-channel, double-frequency mode channel.
(L = 0, R = 1)
Serial Data Input Format. Select the input format as follows:
000 = Left-justified
2
001 = I S
010 = Reserved
011 = Reserved
100 = Right-justified, 24-bits
101 = Right-justified, 20-bits
110 = Right-justified, 18-bits
111 = Right-justified, 16-bits
Standalone Mode Enable. When this bit is set (=1), the trans-
mitter is in standalone mode. In this mode the transmitter
inserts block start bits automatically. Channel status bits and
user bits are taken from the respective buffers. Valid bit is set
based on bits 10 and 11 in this DITCTL register for channel
A and B respectively. Bits received with serial data are ignored.
When this bit is cleared (=0), the transmitter is in full serial
mode. In this mode, all the status bits, including the block
start bit, (indicating start of a frame) come through the
SDATA pin along with audio data. The transmitter should be
enabled after or with all other control bits.
Validity Bit A. Use with channel status buffer.
Validity Bit B. Use with channel status buffer.
Block Status (read-only). Status bit that indicates block start
(when bit 9, DIT_AUTO, = 1).
0 = Current word is not block start
1 = Current word is block start
ADSP-21368 SHARC Processor Hardware Reference