Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 170

SDRAM Controller
In order to set up the SDC and start the SDRAM power-up sequence for
the SDRAMs, use the following procedure. Note that the registers must be
programmed in order.
1. External port control (
SDC)
2. Refresh rate control (
3. SDRAM control (
and SDRAM based on speed and SDRAM specs)
4. Access to SDRAM address space (initiates power-up sequence)
The bit (bit 3) of the SDRAM control status register can be checked
SDRS
to determine the current state of the SDC. If this bit is set, the SDRAM
power-up sequence has not been initiated.
In order to set up the SDC and start the SDRAM power-up sequence for
the SDRAMs, the SDRAM refresh rate control register (
SDRAM memory control register (
must be started to SDRAM address space. The
control status register can be checked to determine the current state of the
SDC. If this bit is set, the SDRAM power-up sequence has not been
initiated.
The field of the
RDIV
rate.
Write to the
SDCTL
• Set the SDRAM cycle timing options—
,
SDTRCD
• Enable the SDRAM clock (
• Set the data path width (
3-62
EPCTL
SDRRC
) register (define global control for SDC
SDCTL
register ia written to set the SDRAM refresh
SDRRC
register in order to:
,
SDTWR SDBUF
X16DE
ADSP-21368 SHARC Processor Hardware Reference
) register (assign external banks to
) register (program refresh counter)
) must be written, and a transfer
SDCTL
bit of the SDRAM
SDRS
,
SDCL
)
DSDCTL
)
) and
SDRRC
, ,
SDTRAS SDTRP