Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 270

DAI/DPI Interrupt Controller
DPI_IRPTL_FE
signal. A particular interrupt can be latched at the rising or falling edge
independently. Keeping corresponding bits reset in both these registers
(
DPI_IRPTL_RE
The
DPI_INT
register is read for the
mode only) interrupts. Furthermore, the
mode must be cleared in the ISR. For information on using inter-
rupts in the UART, see
"UARTxIIR Register" on page
interrupts in the TWI, see
page 12-7
The UART and TWI interrupts are only used as rising edge interrupts.
The corresponding bits in the
default, at reset, all interrupts are disabled (in other words, both the
DPI_IRPTL_RE
Interrupt service routines (ISR) must read the
cover all of the interrupts that are currently latched. A shadow register,
, is provided for the primary register
DPI_IRPTL_SH
this register returns data in the
contents of the register.
Note that the ISR must make sure that the current interrupt condition is
removed before exiting to the main program. Further note that for the
interrupts corresponding to the UART and the TWI, the bits in the
DPI_IRPTL_RE
the
DPI_IRPTL_FE
4-68
register enables interrupt latching at the falling edge of that
and
DPI_IRPTL_FE
interrupt is automatically cleared when the
EXT_MISC
"UARTxIER Register" on page
and "Interrupt Enable Register" on page
DPI_IRPTL_FE
and
DPI_IRPTL_FE
DPI_IRPTL
register are used as enable bits and corresponding bits from
register are not used.
ADSP-21368 SHARC Processor Hardware Reference
) disables the corresponding interrupt.
, , and
UART_TX
UART_RX
11-9. For information on using
"Interrupt Source Register" on
register are reserved. By
registers have zero values).
DPI_IRPTL
DPI_IRPTL
register without clearing the
DPI_IRPTL
(for DMA
UART_RX
interrupt for I/O
11-7, and
12-8.
register to dis-
. Reads of