Master Status Register (Twimstat - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Two Wire Interface Registers

Master Status Register (TWIMSTAT)

The TWI master mode status register (
and described in
transfers and at their conclusions. Generally, master mode status bits are
not directly associated with the generation of interrupts but offer informa-
tion on the current transfer. Slave mode operation does not affect master
mode status bits. This is a read-only register.
TWIMSTAT (0x4418)
15 14 13 12 11 10
0
TWIBUSY
Bus Busy
0=The bus is free
1=The bus is busy
TWISCLSEN
Serial Clock Sense
0=An inactive 1 is sensed on SCLK
1=An active 0 is sensed on SCLK
TWISDASEN
Serial Data Sense
0 =An inactive 1 is sensed on serial data line
1=An active 0 is sensed on serial data line
TWIWERR
Buffer Write Error
0=Buffer write error not detected
1=Transfer aborted due to receive buffer write error
TWIRERR
Buffer Read Error
0=Buffer read error not detected
1=Transfer aborted due to transmit buffer read error
Figure A-64. Master Mode Status Register
A-140
Table A-58) holds information during master mode
9 8 7
0 0 0 0 0 0 0 0
ADSP-21368 SHARC Processor Hardware Reference
, shown in
TWIMSTAT
6 5 4 3 2 1 0
0 0 0 0 0 0 0
Figure A-64
TWIMPROG
Master Tx in Progress
0=No transfer is taking place
1=Master transfer is in progress
TWILOST
Lost Arbitration
0=Transfer has not lost arbitration
1=Current transfer aborted
TWIANAK
Address Not Acknowledged
0=Transfer has not detected a NAK
during addressing
1=Transfer was aborted
TWIDNAK
Data Not Acknowledged
0=Transfer has not detected a NAK
1=Transfer was aborted