Read/Write - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Read/Write

This command is executed if the next read/write access is in the present
active page. During the read command, the SDRAM latches the column
address. The delay between activate and read commands is determined by
the t parameter. Data is available from the SDRAM after the CAS
RCD
latency has been met.
In the write command, the SDRAM latches the column address. The
write data is also valid in the same cycle. The delay between activate and
write commands is determined by the t
The SDC does not use the auto-precharge function of SDRAMs, which is
enabled by asserting
Figure 3-10 and
the ADSP-21367/8/9 processors respectively.
Figure 3-13 show the SDRAM write and read timing for the ADSP-2137x
processors.
SDCLK
SDA10
COMMAND ACT
ROW
ADDR
A
BA[1:0]
DATA
Figure 3-10. Write Timing Diagram ADSP-21367/8/9
ADSP-21368 SHARC Processor Hardware Reference
high during a read or write command.
SDA10
Figure 3-11 show the SDRAM write and read timing of
NOP WR WR
COL COL
A A
D D
t RCD
t RAS
parameter.
RCD
Figure 3-12
WR WR NOP
COL COL
A A
D D
t WR
t RC
External Port
and
PRE
NOP ACT
ROW
A
t RP
3-67