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Making Connections in the SRUs
3. Setting
low, not
Setting
logic low, not
SRU_CLK0 (0x2430)
Reserved
SPORT5_CLK_I
Serial Port 5 Clock Input
SPORT3_CLK_I
SPORT2_CLK_I
Serial Port 2 Clock Input
Figure 4-12. SRU_CLK0 Register
4-20
SRU_CLK4[4:0]
PCG_CLKA_O
SRU_CLK4[9:5]
PCG_CLKB_O
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
1
0
0
1
0
15 14 13 12 11 10
9
8
0
0
1
1
0
0
0
0
ADSP-21368 SHARC Processor Hardware Reference
= 0x1C connects
.
= 0x1D connects
.
1
0
0
1
0
0
1
1
7
6
5
4
3
2
1
1
1
0
0
0
0
1
to logic
PCG_EXTA_I
to
PCG_EXTB_I
Reset = 0x252630C2
0
SPORT3_CLK_I
Serial Port 3 Clock Input
SPORT4_CLK_I
Serial Port 4 Clock Input
0
0
SPORT0_CLK_I
Serial Port 0 Clock Input
SPORT1_CLK_I
Serial Port 1 Clock Input
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