Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 162

SDRAM Controller
Table 3-22. 32-Bit Column, Row, and Bank Address Mapping
(1K Words) (Cont'd)
Pin Column Address
SDA10
A[10] IA[9]
A[9] IA[8]
A[8] IA[7]
A[7] IA[6]
A[6] IA[5]
A[5] IA[4]
A[4] IA[3]
A[3] IA[2]
A[2] IA[1]
A[1] IA[0]
A[0] Not USED for 32-bit SDRAMs
In Table 3-23,
= 11 (11 bits).
SDCAW[1:0]
Table 3-23. 32-Bit Column, Row and Bank Address Mapping
(2K Words)
Pin
A[18]
A[17]
A[13]
A[12]
SDA10
A[10]
3-54
Row Address
IA[20]
IA[19]
IA[18]
IA[17]
IA[16]
IA[15]
IA[14]
IA[13]
IA[12]
IA[11]
IA[10]
= 0,
X16DE SDRAW[2:0]
Column Address Row Address
IA[10] IA[22]
IA[21]
IA[9] IA[20]
ADSP-21368 SHARC Processor Hardware Reference
Bank Address
= id 100 (12 bits), and
Bank Address
IA[24]
IA[23]
Pins of SDRAM
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Pins of SDRAM
BA[1]
BA[0]
A[12]
A[11]
A[10]
A[9]