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SRU_PBEN3 (0x247B)
Reserved
PBEN20_I
DAI Port 20 Pin Buffer Enable Input
PBEN18_I
DAI Port 18 Pin Buffer Enable Input
PBEN17_I
DAI Port 17 Pin Buffer Enable Input
Figure 4-40. SRU_PBEN3
Table 4-9. Group F Sources—Pin Output Enable
Selection Code
000000 (0x0)
000001 (0x1)
000010 (0x2)
000011 (0x3)
000100 (0x4)
000101 (0x5)
000110 (0x6)
000111 (0x7)
001000 (0x8)
001001 (0x9)
001010 (0xA)
001011 (0xB)
001100 (0xC)
ADSP-21368 SHARC Processor Hardware Reference
Digital Audio/Digital Peripheral Interfaces
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
1
1
0
15 14 13 12 11 10
9
8
1
1
1
1
0
1
1
1
Source Signal
LOW
HIGH
MISCA0_O
MISCA1_O
MISCA2_O
MISCA3_O
MISCA4_O
MISCA5_O
SPORT0_CLK_PBEN_O
SPORT0_FS_PBEN_O
SPORT0_DA_PBEN_O
SPORT0_DB_PBEN_O
SPORT1_CLK_PBEN_O
1
0
1
1
1
0
0
0
7
6
5
4
3
2
1
1
0
0
1
1
0
1
Description (Output Source)
Select logic level low (0)
Select logic level high (1)
Assign miscellaneous control A0 output to a pin
Assign miscellaneous control A1 output to a pin
Assign miscellaneous control A2 output to a pin
Assign miscellaneous control A3 output to a pin
Assign miscellaneous control A4 output to a pin
Assign miscellaneous control A5 output to a pin
Select serial port 0 clock output enable
Select serial port 0 frame sync output enable
Select serial port 0 data channel A output enable
Select serial port 0 data channel B output enable
Select serial port 1 clock output enable
Reset = 0x1D71F79B
1
PBEN18_I
DAI Port 18
Pin Buffer Enable Input
PBEN19_I
DAI Port 19
Pin Buffer Enable Input
0
1
PBEN16_I
DAI Port 16
Pin Buffer Enable Input
4-49
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