Analog Devices SHARC ADSP-21368 Hardware Reference Manual page 402

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Table of Contents

SPI Transfer Formats

bit defines when the receive buffer can be read. The

defines when the transmit buffer can be filled. The end of a single word

transfer occurs when the

been received and latched into the receive buffer,

shortly after the last sampling edge of

few core clock cycles and is independent of

rate. If configured to generate an interrupt when

= 00), the interrupt becomes active one core clock cycle after

set. When not relying on this interrupt, the end of a transfer can be

detected by polling the

To maintain software compatibility with other SPI devices, the SPI trans-

fer finished bit (

slightly different behavior from that of other commercially available

devices. For a slave device,

is set one-half of the

regardless of

The baud rate determines when the

set, and consequently before new data has been latched into the

buffer. Therefore, for

bit to be set (after

bit is set. This indicates that a new word has

) is also available for polling. This bit may have

is set at the same time as

is set after

ADSP-21368 SHARC Processor Hardware Reference

. The latency is typically a

period after the last

bit is set. In general, when

bit is set before the

= 3, the processor must wait

is set) before reading the

is set before

, and the baud

. For a master

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