Dsp Subsystem Reset, Clocking, Idle Control, And Boot - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Reset, Clocking, Idle Control, and Boot

12 DSP Subsystem Reset, Clocking, Idle Control, and Boot
12.1 Reset Control
12.1.1 Hardware (Cold) Resets
12.1.2 Software (Warm) Resets
216 DSP Subsystem
The DSP subsystem can be reset through hardware or software. The following
sections provide a brief overview of the different sources which generate
hardware and software reset signals for the DSP subsystem.
Complete information on OMAP hardware and software reset control can be
found in the OMAP5910 Dual-Core Processor Clock Generation and System
Reset Management Reference Guide (SPRU678) or the OMAP5912
Multimedia Processor Initialization Reference Guide (SPRU752).
OMAP5912 and OMAP5910 devices have external pins which can be used to
generate hardware resets. On the OMAP5910/5912 devices, these pins
include PWRON_RESET and MPU_RST, The OMAP5912 device also has the
RTC_ON_NOFF pin. Activating any of these pins will reset the DSP
subsystem modules, including the DSP MMU, TIPB, and MPUI.
The OMAP clock generation and system reset module manages the software
reset signals of the DSP subsystem. The MPU-Reset-Control-1 register
(ARM_RSTCT1) can generate three types of software resets that affect the
DSP subsystem. These software resets are:
Global software reset.
-
The DSP, the MPU, and all internal modules are reset when the SW_RST
bit is set.
DSP interface modules reset.
-
The priority registers (TIPB), EMIF configuration registers, and MPUI
control logic (partially) of the DSP subsystem are reset when the
DSP_RST bit is cleared.
DSP subsystem (excluding interface modules) reset.
-
The modules within the DSP subsystem (excluding the interface modules)
are reset when the DSP_EN bit is cleared. The DSP_EN bit must be
cleared after a cold reset to take the DSP subsystem out of reset.
SPRU890A