Pin States In Idle Cycle - Renesas H8S/2633 Series Hardware Manual

T
p
EXTAL
Address
RD
HWR
RAS
CAS, LCAS
Data bus
Figure 7-37 (b) Example Idle Cycle Operation in RAS Down Mode (ICIS0=1)
7.8.2

Pin States in Idle Cycle

Table 7-8 shows pin states in an idle cycle.
Table 7-8 Pin States in Idle Cycle
Pins Pin State
A23 to A0 Contents of next bus cycle
D15 to D0 High impedance
CSn
High*
CAS
High
AS
High
RD
High
HWR
High
LWR
High
DACKn
High
Note: * Remains low in DRAM space RAS down mode or a refresh cycle.
232
DRAM space read
T T T
r c1 c2
External read
T T T T
1 1 2
DRAM space read
T T T
3 c1 c1 c2
Idle cycle