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Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOC3 IOC2 IOC1 IOC0 Description
3
0
0
1
1
0
1
Note:
*1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
538
0
0
TGR3C is Output disabled
output
1
compare
0
1
register*
1
0
0
1
1
0
1
0
0
TGR3C is
input
1
capture
*
1
register*
*
*
Initial output is 0
0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
Output disabled
Initial output is 1
0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input
Input capture at rising edge
source is
Input capture at falling edge
TIOCC3 pin
1
Input capture at both edges
Capture input
Input capture at TCNT4
source is channel
count-up/count-down
4/count clock
(Initial value)
*: Don't care
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