Renesas H8S/2633 Series Hardware Manual page 284

(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 7-35.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
T
1
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
(a) Idle cycle not inserted
(ICIS1 = 0)
Figure 7-35 Relationship between Chip Select (CS) and Read (RD)
230
Bus cycle B
T T T T
2 3 1 2
Data
Long output
collision
floating time
Bus cycle A
T
1
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Bus cycle B
T T T T
2 3 I 1
T
2