Dds=0 - Renesas H8S/2633 Series Hardware Manual

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DDS=0

When the DRAM space is accessed in DMAC single address mode, always perform full access

(normal access). The DACK output level changes to Low afer the T

DRAM interface.

In other than DMAC signle address mode, burst access is possible when the DRAM space is

Figure 7-31 shows the DACK output timing for the DRAM interface when DDS=0.

Note: n = 2 to 5

Figure 7-31 DACK Output Timing when DDS=0 (Example Showing DRAM Access)

state in the case of the