Renesas H8S/2633 Series Hardware Manual page 45

15.2.3 Reset Control/Status Register (RSTCSR) ........................................................... 680
15.2.4 Pin Function Control Register (PFCR) ............................................................... 681
15.2.5 Notes on Register Access .................................................................................... 682
15.3 Operation .......................................................................................................................... 684
15.3.1 Watchdog Timer Operation................................................................................. 684
15.3.2 Interval Timer Operation..................................................................................... 686
15.3.3 Timing of Setting Overflow Flag (OVF)............................................................. 686
15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ........................ 687
15.4 Interrupts........................................................................................................................... 688
15.5 Usage Notes ...................................................................................................................... 688
15.5.1 Contention between Timer Counter (TCNT) Write and Increment .................... 688
15.5.2 Changing Value of PSS and CKS2 to CKS0....................................................... 689
15.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode............... 689
15.5.4 System Reset by WDTOVF Signal..................................................................... 689
15.5.5 Internal Reset in Watchdog Timer Mode ............................................................ 689
15.5.6 OVF Flag Clearing in Interval Timer Mode ....................................................... 690
Section 16 Serial Communication Interface (SCI, IrDA)
(The H8S/2695 is not equipped with an IrDA function)
16.1 Overview........................................................................................................................... 691
16.1.1 Features ............................................................................................................... 691
16.1.2 Block Diagram..................................................................................................... 693
16.1.3 Pin Configuration ................................................................................................ 694
16.1.4 Register Configuration ........................................................................................ 695
16.2 Register Descriptions........................................................................................................ 697
16.2.1 Receive Shift Register (RSR).............................................................................. 697
16.2.2 Receive Data Register (RDR) ............................................................................. 697
16.2.3 Transmit Shift Register (TSR)............................................................................. 698
16.2.4 Transmit Data Register (TDR) ............................................................................ 698
16.2.5 Serial Mode Register (SMR)............................................................................... 699
16.2.6 Serial Control Register (SCR)............................................................................. 702
16.2.7 Serial Status Register (SSR)................................................................................ 706
16.2.8 Bit Rate Register (BRR)...................................................................................... 710
16.2.9 Smart Card Mode Register (SCMR) ................................................................... 719
16.2.10 IrDA Control Register (IrCR) ............................................................................. 720
16.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC)................... 721
16.3 Operation .......................................................................................................................... 723
16.3.1 Overview ............................................................................................................. 723
16.3.2 Operation in Asynchronous Mode....................................................................... 726
16.3.3 Multiprocessor Communication Function........................................................... 737
16.3.4 Operation in Clocked Synchronous Mode .......................................................... 745
16.3.5 IrDA Operation ................................................................................................... 753
16.4 SCI Interrupts ................................................................................................................... 756
16.5 Usage Notes ...................................................................................................................... 758
................... 691
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