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Channel B
Bit 3
Bit 2
Bit 1
DTF3
DTF2
DTF1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the
highest-priority channel according to the relative channel priorities. For relative channel priorities,
see section 8.5.13, DMAC Multi-Channel Operation.
Bit 0
DTF0
Description
0
—
1
Activated by A/D converter conversion end interrupt
Activated by DREQ pin falling edge input*
0
Activated by DREQ pin low-level input
1
0
Activated by SCI channel 0 transmit-data-empty interrupt
1
Activated by SCI channel 0 reception complete interrupt
0
Activated by SCI channel 1 transmit-data-empty interrupt
1
Activated by SCI channel 1 reception complete interrupt
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
Activated by TPU channel 3 compare match/input capture
A interrupt
0
Activated by TPU channel 4 compare match/input capture
A interrupt
1
Activated by TPU channel 5 compare match/input capture
A interrupt
0
—
1
—
(Initial value)
253
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