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A23 to A0
CS
AS
RD
RAS
CAS
BREQ
BACK
Figure 7-40 Example Bus Release Transition Timing After DRAM Access (Reading
7.10.5
Notes
The external bus release function is deactivated when MSTPCR is set to H'FFFFFF or H'EFFFFF
and a transition is made to sleep mode. To use the external bus release function in sleep mode, do
not set MSTPCR to H'FFFFFF and H'EFFFFF.
When the CBRM bit is set to 1 to use the CBR refresh function, set the BREQ=1 width greater
than the number of the slowest external access states. Otherwise, CBR refresh requests from the
refresh timer may not be performed.
DRAM space read access
DRAM)
External bus released
237
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