Pin Function Control Register (Pfcr) - Renesas H8S/2633 Series Hardware Manual

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port
0
Wait input by WAIT pin enabled
1
7.2.6

Pin Function Control Register (PFCR)

Bit : 7
CSS07
Initial value : 0
R/W : R/W
Note: * This function is not available in the H8S/2695. Only 0 should be written to the BUZZE
and LCASS bits.
PFCR is an 8-bit read/write register that controls the CS selection of pins PG4 and PG1, controls
LCAS selection of pins PF2 and PF6, and controls the address output in expanded mode with
ROM.
PFCR is initialized to H'0D/H'00 by a power-on reset and in hardware standby mode. It retains its
previous state by a manual reset or in software standby mode.
Bit 7—CS0/CS7 Select (CSS07): This bit selects the contents of CS output via the PG4 pin. In
modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS.
Bit 7
CSS07 Description
Selects CS0
0
Selects CS7
1
Bit 6—CS3/CS6 Select (CSS36): This bit selects the contents of CS output via the PG1 pin. In
modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS.
Bit 6
CSS36 Description
Selects CS3
0
Selects CS6
1
180
6 5
BUZZE * LCASS *
CSS36
0 0
R/W R/W R/W
4 3 2
AE3 AE2
0 1/0 1/0
R/W R/W
(Initial value)
1 0
AE1 AE0
0 1/0
R/W R/W
(Initial value)
(Initial value)