Renesas H8S/2633 Series Hardware Manual page 904

Table 18-7 Permissible SCL Rise Time (t
t
cyc
IICX Indication
0 7.5t Standard
cyc
mode
High-speed
mode
1 17.5t Standard
cyc
mode
High-speed
mode
• The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
and 300 ns. The I
shown in table 18-6. However, because of the rise and fall times, the I
specifications may not be satisfied at the maximum transfer rate. Table 18-8 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
t fails to meet the I
BUFO
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of
a stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
850
2
I C Bus
Specification ø =
(Max.) 5 MHz
1000 ns 1000 ns 937 ns
300 ns 300 ns
1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns
300 ns 300 ns
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either
in standard mode fail to satisfy the I
STASO
) Values
Sr
Time Indication
ø = ø =
8 MHz 10 MHz
750 ns 468 ns
300 ns 300 ns 300 ns
300 ns 300 ns 300 ns
/t . Possible solutions that should be
Sr Sf
ø = ø = ø =
16 MHz 20 MHz 25 MHz
375 ns 300 ns
300 ns 300 ns
700 ns
300 ns 300 ns
and t
Scyc
2
C bus interface
2
C bus.
2
C bus interface
ø =
28 MHz
267 ns
300 ns
624 ns
300 ns
, as
cyc
2
C