7.2 Register Configuration - Renesas H8S/2633 Series Hardware Manual

10A.7.2 Register Configuration
Table 10A-10 shows the port A register configuration.
Table 10A-10 Port A Registers
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Notes: *1 Lower 16 bits of the address.
*2 Value of bits 3 to 0.
Port A Data Direction Register (PADDR)
Bit : 7
—
Initial value :
Undefined Undefined Undefined Undefined
R/W : —
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 and 6 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is
used to select whether the address output pins retain their output state or become high-impedance
when a transition is made to software standby mode.
• Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA4DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
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Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
6 5 4
— — —
— — —
Initial Value *
R/W
W H'0
R/W H'0
R Undefined
R/W H'0
R/W H'0
3 2
PA3DDR PA2DDR PA1DDR PA0DDR
0 0
W W
2 Address * 1
H'FE39
H'FF09
H'FFB9
H'FE40
H'FE47
1 0
0 0
W W