Renesas H8S/2633 Series Hardware Manual page 35

5.1.1 Features ............................................................................................................... 121
5.1.2 Block Diagram..................................................................................................... 122
5.1.3 Pin Configuration ................................................................................................ 123
5.1.4 Register Configuration ........................................................................................ 123
5.2 Register Descriptions........................................................................................................ 124
5.2.1 System Control Register (SYSCR) ..................................................................... 124
5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) ............................ 125
5.2.3 IRQ Enable Register (IER) ................................................................................. 126
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................... 127
5.2.5 IRQ Status Register (ISR) ................................................................................... 128
5.3 Interrupt Sources............................................................................................................... 129
5.3.1 External Interrupts............................................................................................... 129
5.3.2 Internal Interrupts ................................................................................................ 130
5.3.3 Interrupt Exception Handling Vector Table ........................................................ 130
5.4 Interrupt Operation ........................................................................................................... 139
5.4.1 Interrupt Control Modes and Interrupt Operation ............................................... 139
5.4.2 Interrupt Control Mode 0..................................................................................... 142
5.4.3 Interrupt Control Mode 2..................................................................................... 144
5.4.4 Interrupt Exception Handling Sequence ............................................................. 146
5.4.5 Interrupt Response Times.................................................................................... 147
5.5 Usage Notes ...................................................................................................................... 148
5.5.1 Contention between Interrupt Generation and Disabling.................................... 148
5.5.2 Instructions that Disable Interrupts ..................................................................... 149
5.5.3 Times when Interrupts are Disabled ................................................................... 149
5.5.4 Interrupts during Execution of EEPMOV Instruction......................................... 150
5.6 DTC and DMAC Activation by Interrupt
(DMAC and DTC functions are not available in the H8S/2695) ..................................... 150
5.6.1 Overview ............................................................................................................. 150
5.6.2 Block Diagram..................................................................................................... 150
Operation (DMAC and DTC functions are not available in the H8S/2695)....... 151
5.6.3
Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695)
6.1 Overview........................................................................................................................... 153
6.1.1 Features ............................................................................................................... 153
6.1.2 Block Diagram..................................................................................................... 154
6.1.3 Register Configuration ........................................................................................ 155
6.2 Register Descriptions........................................................................................................ 155
6.2.1 Break Address Register A (BARA) .................................................................... 155
6.2.2 Break Address Register B (BARB)..................................................................... 156
6.2.3 Break Control Register A (BCRA) ..................................................................... 156
6.2.4 Break Control Register B (BCRB) ...................................................................... 158
6.2.5 Module Stop Control Register C (MSTPCRC)................................................... 158
................................. 153
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