Renesas H8S/2633 Series Hardware Manual page 11

Section
4.4 Interrupts
5.1.1 Features
5.2.2 Interrupt Priority
Registers A to L, O
(IPRA to IPRL, IPRO)
5.2.5 IRQ Status
Register (ISR)
5.3.1 External
Interrupts
5.3.2 Internal
Interrupts
5.3.3 Interrupt
Exception Handling
Vector Table
5.6 DTC and DMAC
Activation by Interrupt
(DMAC and DTC
functions are not
available in the
H8S/2695)
5.6.2 Block Diagram
5.6.3 Operation
(DMAC and DTC
functions are not
available in the
H8S/2695)
Page Item
117
Figure 4-4 Interrupt Sources
and Number of Interrupts
121 • DTC and DMAC control
125 Table 5-3 Correspondence
between Interrupt Sources
and IPR Settings
128 Bits 7 to 0—IRQ7 to IRQ0 flags
(IRQ7F to IRQ0F)
129
130
131 to 134 Table 5-4(a) Interrupt
Sources, Vector Addresses,
and Interrupt Priorities
(H8S/2633, H8S/2632,
H8S/2631, H8S/2633R)
135 to 138 Table 5-4(b) Interrupt
Sources, Vector Addresses,
and Interrupt Priorities
(H8S/2695)
150
151 Figure 5-9 Interrupt Control
for DTC and DMAC
152 Table 5-11 Interrupt Source
Selection and Clearing Control
(4) Notes on Use
Description
Note * added
Note *3 added
Note * added
Note * added
(n = 5 to 0) amended to
(n = 7 to 0)
IRQ7 to IRQ0 Interrupts
IRQ5 to IRQ0 amended to
IRQ7 to IRQ0
Notes *1 and *2 added
H8S/2633R added
Amend as follows:
Interrupt Source column:
"CMI" → "Reserved"
Origin of Interrupt Source
column: "Refresh timer" →
""
Newly added
Title amended
Note * added
Note *1 added
Note * added
3