Renesas H8S/2633 Series Hardware Manual page 886

Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and
generates the stop condition.
Generate start
condition
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
ICDRE
IRIC
IRTR
ICDRT
ICDRS
Note: ICDR data
setting timing
Improper operation will
result.
User processing [4] Write BBSY = 1
and SCP = 0
(generate start
condition)
Figure 18-8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)
SCL
8
(Master output)
SDA
Bit 0
(Master output)
[7]
Data 1
SDA
(Slave output)
ICDRE
IRIC
IRTR
Data 1
ICDR
User processing
Figure 18-9 Example of Master Transmit Mode Stop Condition Generation Timing
832
1 2
Bit 7 Bit 6 Bit 5
[5]
Interrupt
request
Address + R/W
Address + R/W
Normal operation
[6] ICDR write
9 1 2
Bit 7 Bit 6
A
[9] ICDR write [9] IRIC clearance
(MLS = WAIT = 0)
3 4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1
Slave address
[6] IRIC clearance
3 4 5 6 7
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 2
Data 2
8 9 1
Bit 0 Bit 7
[7]
R/W
A
Interrupt
request
Data 1
Data 1
[9] ICDR write [9] IRIC clearance
Generate start
condition
8 9
[10]
A
[12] Write BBSY = 0
[11] ACKB read
and SCP = 0
(generate stop
condition)
[12] IRIC clearance
2
Bit 6
Data 1