Renesas H8S/2633 Series Hardware Manual page 38

8.2.2 I/O Address Register (IOAR).............................................................................. 249
8.2.3 Execute Transfer Count Register (ETCR)........................................................... 249
8.2.4 DMA Control Register (DMACR)...................................................................... 250
8.2.5 DMA Band Control Register (DMABCR).......................................................... 254
8.3 Register Descriptions (2) (Full Address Mode) ............................................................... 259
8.3.1 Memory Address Register (MAR) ...................................................................... 259
8.3.2 I/O Address Register (IOAR).............................................................................. 259
8.3.3 Execute Transfer Count Register (ETCR)........................................................... 260
8.3.4 DMA Control Register (DMACR)...................................................................... 261
8.3.5 DMA Band Control Register (DMABCR).......................................................... 265
8.4 Register Descriptions (3) .................................................................................................. 270
8.4.1 DMA Write Enable Register (DMAWER) ......................................................... 270
8.4.2 DMA Terminal Control Register (DMATCR).................................................... 272
8.4.3 Module Stop Control Register (MSTPCR) ......................................................... 273
8.5 Operation .......................................................................................................................... 274
8.5.1 Transfer Modes ................................................................................................... 274
8.5.2 Sequential Mode.................................................................................................. 276
8.5.3 Idle Mode............................................................................................................. 279
8.5.4 Repeat Mode ....................................................................................................... 282
8.5.5 Single Address Mode .......................................................................................... 286
8.5.6 Normal Mode....................................................................................................... 289
8.5.7 Block Transfer Mode........................................................................................... 292
8.5.8 DMAC Activation Sources ................................................................................. 298
8.5.9 Basic DMAC Bus Cycles .................................................................................... 301
8.5.10 DMAC Bus Cycles (Dual Address Mode) .......................................................... 302
8.5.11 DMAC Bus Cycles (Single Address Mode) ....................................................... 310
8.5.12 Write Data Buffer Function................................................................................. 316
8.5.13 DMAC Multi-Channel Operation ....................................................................... 317
8.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC,
and the DMAC .................................................................................................... 319
8.5.15 NMI Interrupts and DMAC................................................................................. 320
8.5.16 Forced Termination of DMAC Operation........................................................... 321
8.5.17 Clearing Full Address Mode ............................................................................... 322
8.6 Interrupts........................................................................................................................... 323
8.7 Usage Notes ...................................................................................................................... 324
Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
9.1 Overview........................................................................................................................... 329
9.1.1 Features ............................................................................................................... 329
9.1.2 Block Diagram..................................................................................................... 330
9.1.3 Register Configuration ........................................................................................ 331
9.2 Register Descriptions........................................................................................................ 332
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................................. 329