Renesas H8S/2633 Series Hardware Manual page 733

WDT1 * 1
Input Clock Select
Bit 4 Bit 2 Bit 1
PSS CKS2 CKS1
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Notes: *1 WDT1 is not available in the H8S/2695.
*2 An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
Description
Bit 0
CKS0 Clock
0 ø/2 (Initial value)
1 ø/64
0 ø/128
1 ø/512
0 ø/2048
1 ø/8192
0 ø/32768
1 ø/131072
0 øSUB/2
1 øSUB/4
0 øSUB/8
1 øSUB/16
0 øSUB/32
1 øSUB/64
0 øSUB/128
1 øSUB/256
2
Overflow Period* (where ø = 25 MHz)
(where ø SUB = 32.768 kHz)
20.4 µs
655.3 µs
1.3 ms
5.2 ms
20.9 ms
83.8 ms
335.5 ms
1.34 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
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