Renesas H8S/2633R F-ZTAT Manuals

Manuals and User Guides for Renesas H8S/2633R F-ZTAT. We have 1 Renesas H8S/2633R F-ZTAT manual available for free PDF download: Hardware Manual

Renesas H8S/2633R F-ZTAT Hardware Manual (1453 pages)

Brand: Renesas | Category: Computer Hardware | Size: 8.03 MB

Table of Contents
33
Overview
55
Internal Block Diagram
62
Pin Description
65
Pin Arrangement
65
Pin Functions in each Operating Mode
70
Pin Functions
85
Cpu
103
Overview
103
Features
103
Differences between H8S/2600 CPU and H8S/2000 CPU
104
Differences from H8/300 CPU
105
Differences from H8/300H CPU
106
CPU Operating Modes
106
Address Space
111
Register Configuration
112
Overview
112
General Registers
113
Control Registers
114
Initial Register Values
116
Data Formats
117
General Register Data Formats
117
Memory Data Formats
119
Instruction Set
120
Overview
120
Instructions and Addressing Modes
121
Table of Instructions Classified by Function
123
Basic Instruction Formats
130
Addressing Modes and Effective Address Calculation
132
Addressing Mode
132
Effective Address Calculation
135
Processing States
139
Overview
139
Reset State
140
Exception-Handling State
141
Program Execution State
144
Bus-Released State
144
Power-Down State
144
Basic Timing
145
Overview
145
On-Chip Memory (ROM, RAM)
145
On-Chip Supporting Module Access Timing
147
External Address Space Access Timing
148
Usage Note
148
TAS Instruction
148
MCU Operating Modes
149
Overview
149
Operating Mode Selection
149
Register Configuration
150
Register Descriptions
150
Mode Control Register (MDCR)
150
System Control Register (SYSCR)
151
Pin Function Control Register (PFCR)
153
Operating Mode Descriptions
156
Mode 4
156
Mode 5
157
Mode 6
157
Mode 7
157
Pin Functions in each Operating Mode
157
Address Map in each Operating Mode
157
Exception Handling
163
Overview
163
Exception Handling Types and Priority
163
Exception Handling Operation
164
Exception Vector Table
164
Reset
166
Overview
166
Types of Reset
166
Reset Sequence
167
Interrupts after Reset
169
State of On-Chip Supporting Modules after Reset Release
169
Traces
170
Interrupts
171
Trap Instruction
172
Stack Status after Exception Handling
173
Notes on Use of the Stack
174
Interrupt Controller
175
Overview
175
Features
175
Block Diagram
176
Pin Configuration
177
Register Configuration
177
Register Descriptions
178
System Control Register (SYSCR)
178
Interrupt Priority Registers a to L, O (IPRA to IPRL, IPRO)
179
IRQ Enable Register (IER)
180
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
181
IRQ Status Register (ISR)
182
Interrupt Sources
183
External Interrupts
183
Internal Interrupts
184
Interrupt Exception Handling Vector Table
184
Interrupt Operation
193
Interrupt Control Modes and Interrupt Operation
193
Interrupt Control Mode 0
196
Interrupt Control Mode 2
198
Interrupt Exception Handling Sequence
200
Interrupt Response Times
201
Usage Notes
202
Contention between Interrupt Generation and Disabling
202
Instructions that Disable Interrupts
203
Times When Interrupts Are Disabled
203
Interrupts During Execution of EEPMOV Instruction
204
DTC and DMAC Activation by Interrupt (DMAC and DTC Functions Are Not Available in the H8S/2695)
204
Overview
204
Block Diagram
204
Operation (DMAC and DTC Functions Are Not Available in the H8S/2695)
205
PC Break Controller (PBC)
207
(This Function Is Not Available in the H8S/2695)
207
Overview
207
Features
207
Block Diagram
208
Register Configuration
209
Register Descriptions
209
Break Address Register a (BARA)
209
Break Address Register B (BARB)
210
Break Control Register a (BCRA)
210
Break Control Register B (BCRB)
212
Module Stop Control Register C (MSTPCRC)
212
Operation
213
PC Break Interrupt Due to Instruction Fetch
213
PC Break Interrupt Due to Data Access
213
Notes on PC Break Interrupt Handling
214
Operation in Transitions to Power-Down Modes
214
PC Break Operation in Continuous Data Transfer
215
When Instruction Execution Is Delayed by One State
216
Additional Notes
217
Bus Controller
219
Overview
219
Features
219
Block Diagram
221
Pin Configuration
222
Register Configuration
223
Register Descriptions
224
Bus Width Control Register (ABWCR)
224
Access State Control Register (ASTCR)
225
Wait Control Registers H and L (WCRH, WCRL)
226
Bus Control Register H (BCRH)
229
Bus Control Register L (BCRL)
232
Pin Function Control Register (PFCR)
234
Memory Control Register (MCR)
237
DRAM Control Register (DRAMCR)
239
Refresh Timer Counter (RTCNT)
241
Refresh Time Constant Register (RTCOR)
241
Overview of Bus Control
242
Area Partitioning
242
Bus Specifications
243
Memory Interfaces
244
Interface Specifications for each Area
245
Chip Select Signals
246
Basic Bus Interface
247
Overview
247
Data Size and Data Alignment
247
Valid Strobes
249
Basic Timing
250
Wait Control
258
DRAM Interface
260
(This Function Is Not Available in the H8S/2695)
260
Overview
260
Setting up DRAM Space
260
Address Multiplexing
261
Data Bus
261
DRAM Interface Pins
262
Basic Timing
262
Precharge State Control
264
Wait Control
265
Byte Access Control
267
Burst Operation
269
Refresh Control
273
DMAC Single Address Mode and DRAM Interface (this Function Is Not Available in the H8S/2695)
277
Dds=1
277
Dds=0
278
Burst ROM Interface
279
Overview
279
Basic Timing
279
Wait Control
281
Idle Cycle
282
Operation
282
Pin States in Idle Cycle
286
Write Data Buffer Function
287
Bus Release
288
Overview
288
Operation
288
Pin States in External Bus Released State
289
Transition Timing
290
Notes
291
Bus Arbitration
292
(DMAC and DTC Functions Are Not Available in the H8S/2695)
292
Overview
292
Operation
292
Bus Transfer Timing
293
Resets and the Bus Controller
293
DMA Controller (DMAC) (this Function Is Not Available in the H8S/2695)
295
Overview
295
Features
295
Block Diagram
296
Overview of Functions
297
Pin Configuration
299
Register Configuration
300
Register Descriptions (1) (Short Address Mode)
301
Memory Address Registers (MAR)
302
I/O Address Register (IOAR)
303
Execute Transfer Count Register (ETCR)
303
DMA Control Register (DMACR)
304
DMA Band Control Register (DMABCR)
308
Register Descriptions (2) (Full Address Mode)
313
Memory Address Register (MAR)
313
I/O Address Register (IOAR)
313
Execute Transfer Count Register (ETCR)
314
DMA Control Register (DMACR)
315
DMA Band Control Register (DMABCR)
319
Register Descriptions (3)
324
DMA Write Enable Register (DMAWER)
324
DMA Terminal Control Register (DMATCR)
326
Module Stop Control Register (MSTPCR)
327
Operation
328
Transfer Modes
328
Sequential Mode
330
Idle Mode
333
Repeat Mode
336
Single Address Mode
340
Normal Mode
343
Block Transfer Mode
346
DMAC Activation Sources
352
Basic DMAC Bus Cycles
355
DMAC Bus Cycles (Dual Address Mode)
356
DMAC Bus Cycles (Single Address Mode)
364
Write Data Buffer Function
370
DMAC Multi-Channel Operation
371
Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
373
NMI Interrupts and DMAC
374
Forced Termination of DMAC Operation
375
Clearing Full Address Mode
376
Interrupts
377
Usage Notes
378
Data Transfer Controller (DTC)
383
(This Function Is Not Available in the H8S/2695)
383
Overview
383
Features
383
Block Diagram
384
Register Configuration
385
Register Descriptions
386
DTC Mode Register a (MRA)
386
DTC Mode Register B (MRB)
388
DTC Source Address Register (SAR)
389
DTC Destination Address Register (DAR)
389
DTC Transfer Count Register a (CRA)
389
DTC Transfer Count Register B (CRB)
390
DTC Enable Registers (DTCER)
390
DTC Vector Register (DTVECR)
391
Module Stop Control Register a (MSTPCRA)
392
Operation
393
Overview
393
Activation Sources
395
DTC Vector Table
396
Location of Register Information in Address Space
400
Normal Mode
401
Repeat Mode
402
Block Transfer Mode
403
Chain Transfer
405
Operation Timing
406
Number of DTC Execution States
407
Procedures for Using DTC
409
Examples of Use of the DTC
410
Interrupts
413
Usage Notes
413
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
415
Overview
415
Port 1
420
2.1 Overview
420
2.2 Register Configuration
421
2.3 Pin Functions
423
Port 3
435
3.1 Overview
435
3.2 Register Configuration
435
3.3 Pin Functions
438
Port 4
441
4.1 Overview
441
4.2 Register Configuration
442
4.3 Pin Functions
442
Port 7
443
5.1 Overview
443
5.2 Register Configuration
444
5.3 Pin Functions
446
Port 9
449
6.1 Overview
449
6.2 Register Configuration
450
6.3 Pin Functions
450
Port a
451
7.1 Overview
451
7.2 Register Configuration
452
7.3 Pin Functions
455
7.4 MOS Input Pull-Up Function
455
Port B
457
8.1 Overview
457
8.2 Register Configuration
458
8.3 Pin Functions
461
8.4 MOS Input Pull-Up Function
462
Port C
463
9.1 Overview
463
9.2 Register Configuration
464
9.3 Pin Functions for each Mode
467
9.4 MOS Input Pull-Up Function
469
10 Port D
470
10.1 Overview
470
10.2 Register Configuration
471
10.3 Pin Functions
473
10.4 MOS Input Pull-Up Function
474
11 Port E
475
11.1 Overview
475
11.2 Register Configuration
476
11.3 Pin Functions
478
11.4 MOS Input Pull-Up Function
479
12 Port F
480
12.1 Overview
480
12.2 Register Configuration
481
12.3 Pin Functions
483
13 Port G
485
13.1 Overview
485
13.2 Register Configuration
486
13.3 Pin Functions
488
Section 10B I/O Ports (H8S/2695)
491
Overview
491
Port 1
496
2.1 Overview
496
2.2 Register Configuration
497
2.3 Pin Functions
499
Port3
511
3.1 Overview
511
3.2 Register Configuration
511
3.3 Pin Functions
514
Port 4
517
4.1 Overview
517
4.2 Register Configuration
518
4.3 Pin Functions
518
Port 7
519
5.1 Overview
519
5.2 Register Configuration
520
5.3 Pin Functions
522
Port 9
524
6.1 Overview
524
6.2 Register Configuration
525
6.3 Pin Functions
525
Port a
526
7.1 Overview
526
7.2 Register Configuration
527
7.3 Pin Functions
530
7.4 MOS Input Pull-Up Function
531
Port B
532
8.1 Overview
532
8.2 Register Configuration
533
8.3 Pin Functions
536
8.4 MOS Input Pull-Up Function
537
Port C
538
9.1 Overview
538
9.2 Register Configuration
539
9.3 Pin Functions for each Mode
542
9.4 MOS Input Pull-Up Function
544
10 Port D
545
10.1 Overview
545
10.2 Register Configuration
546
10.3 Pin Functions
548
10.4 MOS Input Pull-Up Function
549
11 Port E
550
11.1 Overview
550
11.2 Register Configuration
551
11.3 Pin Functions
553
11.4 MOS Input Pull-Up Function
554
12 Port F
555
12.1 Overview
555
12.2 Register Configuration
556
12.3 Pin Functions
558
13 Port G
560
13.1 Overview
560
13.2 Register Configuration
561
13.3 Pin Functions
563
Section 11 16-Bit Timer Pulse Unit (TPU)
565
Overview
565
Features
565
Block Diagram
569
Pin Configuration
570
Register Configuration
572
Register Descriptions
574
Timer Control Register (TCR)
574
Timer Mode Register (TMDR)
579
Timer I/O Control Register (TIOR)
581
Timer Interrupt Enable Register (TIER)
594
Timer Status Register (TSR)
597
Timer Counter (TCNT)
601
Timer General Register (TGR)
602
Timer Start Register (TSTR)
603
Timer Synchro Register (TSYR)
604
Module Stop Control Register a (MSTPCRA)
605
Interface to Bus Master
606
16-Bit Registers
606
Operation
608
Overview
608
Basic Functions
609
Synchronous Operation
615
Buffer Operation
617
Cascaded Operation
621
PWM Modes
623
Phase Counting Mode
628
Interrupts
635
Interrupt Sources and Priorities
635
DTC/DMAC Activation (this Function Is Not Available in the H8S/2695)
637
A/D Converter Activation
637
Operation Timing
638
Input/Output Timing
638
Interrupt Signal Timing
642
Usage Notes
646
Section 12 Programmable Pulse Generator (PPG)
657
(This Function Is Not Available in the H8S/2695)
657
Overview
657
Features
657
Block Diagram
658
Pin Configuration
659
Registers
660
Register Descriptions
661
Next Data Enable Registers H and L (NDERH, NDERL)
661
Output Data Registers H and L (PODRH, PODRL)
662
Next Data Registers H and L (NDRH, NDRL)
663
Notes on NDR Access
663
PPG Output Control Register (PCR)
665
PPG Output Mode Register (PMR)
667
Port 1 Data Direction Register (P1DDR)
670
Module Stop Control Register a (MSTPCRA)
670
Operation
671
Overview
671
Output Timing
672
Normal Pulse Output
673
Non-Overlapping Pulse Output
675
Inverted Pulse Output
678
Pulse Output Triggered by Input Capture
679
Usage Notes
680
Section 13 8-Bit Timers (TMR) (this Function Is Not Available in the H8S/2695)
683
Overview
683
Features
683
Block Diagram
684
Pin Configuration
685
Register Configuration
686
Register Descriptions
687
Timer Counters 0 to 3 (TCNT0 to TCNT3)
687
Time Constant Registers A0 to A3 (TCORA0 to TCORA3)
687
Time Constant Registers B0 to B3 (TCORB0 to TCORB3)
688
Timer Control Registers 0 to 3 (TCR0 to TCR3)
688
Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3)
691
Module Stop Control Register a (MSTPCRA)
694
Operation
695
TCNT Incrementation Timing
695
Compare Match Timing
696
Timing of External RESET on TCNT
698
Timing of Overflow Flag (OVF) Setting
698
Operation with Cascaded Connection
699
Interrupts
700
Interrupt Sources and DTC Activation (the H8S/2695 Does Not Have a DTC Function or an 8-Bit Timer)
700
A/D Converter Activation
700
Sample Application
701
Usage Notes
702
Contention between TCNT Write and Clear
702
Contention between TCNT Write and Increment
703
Contention between TCOR Write and Compare Match
704
Contention between Compare Matches a and B
705
Switching of Internal Clocks and TCNT Operation
705
Interrupts and Module Stop Mode
707
Section 14 14-Bit PWM D/A (this Function Is Not Available in the H8S/2695)
709
Overview
709
Features
709
Block Diagram
710
Pin Configuration
711
Register Configuration
711
Register Descriptions
712
PWM D/A Counter (DACNT)
712
PWM D/A Data Registers a and B (DADRA and DADRB)
713
PWM D/A Control Register (DACR)
714
Module Stop Control Register B (MSTPCRB)
716
Bus Master Interface
717
Operation
720
Section 15 Watchdog Timer (WDT1 Is Not Available in the H8S/2695)
725
Overview
725
Features
725
Block Diagram
726
Pin Configuration
728
Register Configuration
728
Register Descriptions
729
Timer Counter (TCNT)
729
Timer Control/Status Register (TCSR)
729
Reset Control/Status Register (RSTCSR)
734
Pin Function Control Register (PFCR)
735
Notes on Register Access
736
Operation
738
Watchdog Timer Operation
738
Interval Timer Operation
740
Timing of Setting Overflow Flag (OVF)
740
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
741
Interrupts
742
Usage Notes
742
Contention between Timer Counter (TCNT) Write and Increment
742
Changing Value of PSS and CKS2 to CKS0
743
Switching between Watchdog Timer Mode and Interval Timer Mode
743
System Reset by WDTOVF Signal
743
Internal Reset in Watchdog Timer Mode
743
OVF Flag Clearing in Interval Timer Mode
744
Section 16 Serial Communication Interface (SCI, Irda)
745
(The H8S/2695 Is Not Equipped with an Irda Function)
745
Overview
745
Features
745
Block Diagram
747
Pin Configuration
748
Register Configuration
749
Register Descriptions
751
Receive Shift Register (RSR)
751
Receive Data Register (RDR)
751
Transmit Shift Register (TSR)
752
Transmit Data Register (TDR)
752
Serial Mode Register (SMR)
753
Serial Control Register (SCR)
756
Serial Status Register (SSR)
760
Bit Rate Register (BRR)
764
Smart Card Mode Register (SCMR)
773
Irda Control Register (Ircr)
774
Module Stop Control Registers B and C (MSTPCRB, MSTPCRC)
775
Operation
777
Overview
777
Operation in Asynchronous Mode
780
Multiprocessor Communication Function
791
Operation in Clocked Synchronous Mode
799
Irda Operation
807
SCI Interrupts
810
Usage Notes
812
Section 17 Smart Card Interface
821
Overview
821
Features
821
Block Diagram
822
Pin Configuration
823
Register Configuration
824
Register Descriptions
826
Smart Card Mode Register (SCMR)
826
Serial Status Register (SSR)
828
Serial Mode Register (SMR)
830
Serial Control Register (SCR)
832
Operation
833
Overview
833
Pin Connections
833
Data Format
835
Register Settings
837
Clock
839
Data Transfer Operations
841
Operation in GSM Mode
848
Operation in Block Transfer Mode
849
Usage Notes
850
Section 18 I
853
(This Function Is Not Available in the H8S/2695)
853
Overview
853
Features
853
Block Diagram
854
Input/Output Pins
856
Register Configuration
857
Register Descriptions
858
I 2 C Bus Data Register (ICDR)
858
Slave Address Register (SAR)
861
Second Slave Address Register (SARX)
862
I 2 C Bus Mode Register (ICMR)
863
I 2 C Bus Control Register (ICCR)
866
I 2 C Bus Status Register (ICSR)
873
Serial Control Register X (SCRX)
878
DDC Switch Register (DDCSWR)
879
Module Stop Control Register B (MSTPCRB)
880
Operation
881
C Bus Data Format
881
Initial Setting
883
Master Transmit Operation
883
Master Receive Operation
887
Slave Receive Operation
892
Slave Transmit Operation
894
IRIC Setting Timing and SCL Control
896
Operation Using the DTC
897
Noise Canceler
898
Sample Flowcharts
898
Initialization of Internal State
901
Usage Notes
902
Section 19 A/D Converter
913
Overview
913
Features
913
Block Diagram
914
Pin Configuration
915
Register Configuration
916
Register Descriptions
917
A/D Data Registers a to D (ADDRA to ADDRD)
917
A/D Control/Status Register (ADCSR)
918
A/D Control Register (ADCR)
921
Module Stop Control Register a (MSTPCRA)
922
Interface to Bus Master
923
Operation
924
Single Mode (SCAN = 0)
924
Scan Mode (SCAN = 1)
926
Input Sampling and A/D Conversion Time
928
External Trigger Input Timing
929
Interrupts
930
Usage Notes
930
Section 20 D/A Converter (this Function Is Not Available in the H8S/2695)
937
Overview
937
Features
937
Block Diagram
937
Input and Output Pins
939
Register Configuration
939
Register Descriptions
940
D/A Data Registers 0 to 3 (DADR0 to DADR3)
940
D/A Control Register 01 and 23 (DACR01 and DACR23)
940
Module Stop Control Register a and C (MSTPCRA and MSTPCRC)
942
Operation
944
Section 21 RAM
945
Overview
945
Block Diagram
945
Register Configuration
946
Register Descriptions
946
System Control Register (SYSCR)
946
Operation
947
Usage Notes
947
Section 22 ROM
949
Overview
949
Block Diagram
949
Register Configuration
949
Register Descriptions
950
Mode Control Register (MDCR)
950
Operation
950
Flash Memory Overview
953
Features
953
Overview
954
Flash Memory Operating Modes
955
On-Board Programming Modes
956
Flash Memory Emulation in RAM
958
Differences between Boot Mode and User Program Mode
959
Block Configuration
960
Pin Configuration
960
Register Configuration
961
Register Descriptions
961
Flash Memory Control Register 1 (FLMCR1)
961
Flash Memory Control Register 2 (FLMCR2)
964
Erase Block Register 1 (EBR1)
965
Erase Block Register 2 (EBR2)
966
RAM Emulation Register (RAMER)
967
Flash Memory Power Control Register (FLPWCR)
969
Serial Control Register X (SCRX)
969
On-Board Programming Modes
970
Boot Mode
971
User Program Mode
975
Programming/Erasing Flash Memory
977
Program Mode
978
Program-Verify Mode
979
Erase Mode
983
Erase-Verify Mode
983
Protection
985
Hardware Protection
985
Software Protection
986
Error Protection
987
Flash Memory Emulation in RAM
989
Interrupt Handling When Programming/Erasing Flash Memory
991
Flash Memory Programmer Mode
991
Socket Adapter Pin Correspondence Diagram
992
Programmer Mode Operation
994
Memory Read Mode
995
Auto-Program Mode
998
Auto-Erase Mode
1000
Status Read Mode
1002
Status Polling
1003
Programmer Mode Transition Time
1003
Notes on Memory Programming
1004
Flash Memory and Power-Down States
1005
Note on Power-Down States
1005
Flash Memory Programming and Erasing Precautions
1006
Note on Switching from F-ZTAT Version to Mask ROM Version
1011
Section 23A Clock Pulse Generator
1013
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
1013
Overview
1013
1.1 Block Diagram
1013
1.2 Register Configuration
1014
Register Descriptions
1014
2.1 System Clock Control Register (SCKCR)
1014
2.2 Low-Power Control Register (LPWRCR)
1015
Oscillator
1016
3.1 Connecting a Crystal Resonator
1016
3.2 External Clock Input
1019
PLL Circuit
1021
Medium-Speed Clock Divider
1021
Bus Master Clock Selection Circuit
1021
Subclock Oscillator
1022
Subclock Waveform Shaping Circuit
1023
Note on Crystal Resonator
1023
Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695)
1025
Overview
1025
1.1 Block Diagram
1025
1.2 Register Configuration
1026
Register Descriptions
1026
2.1 System Clock Control Register (SCKCR)
1026
2.2 Low-Power Control Register (LPWRCR)
1027
Oscillator
1028
3.1 Connecting a Crystal Resonator
1028
3.2 External Clock Input
1031
PLL Circuit
1033
Medium-Speed Clock Divider
1033
Bus Master Clock Selection Circuit
1034
Subclock Oscillator (this Function Is Not Available in the H8S/2695)
1034
Subclock Waveform Shaping Circuit
1035
Note on Crystal Resonator
1035
Section 24 Power-Down Modes
1037
Overview
1037
Register Configuration
1042
Register Descriptions
1043
Standby Control Register (SBYCR)
1043
System Clock Control Register (SCKCR)
1045
Low-Power Control Register (LPWRCR)
1046
Timer Control/Status Register (TCSR)
1049
Module Stop Control Register (MSTPCR)
1050
Medium-Speed Mode
1051
Sleep Mode
1052
Exiting Sleep Mode
1052
Module Stop Mode
1053
Usage Notes
1055
Software Standby Mode
1055
Exiting Software Standby Mode
1055
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
1056
Software Standby Mode Application Example
1057
Usage Notes
1058
Hardware Standby Mode
1059
Hardware Standby Mode Timing
1059
Watch Mode
1060
(This Function Is Not Available in the H8S/2695)
1060
Exiting Watch Mode
1060
Notes
1061
Sub-Sleep Mode
1061
(This Function Is Not Available in the H8S/2695)
1061
Exiting Sub-Sleep Mode
1062
Sub-Active Mode
1062
(This Function Is Not Available in the H8S/2695)
1062
Exiting Sub-Active Mode
1062
Usage Notes
1063
Direct Transitions (this Function Is Not Available in the H8S/2695)
1064
Overview of Direct Transitions
1064
Clock Output Disabling Function
1064
Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
1065
Absolute Maximum Ratings
1065
DC Characteristics
1066
AC Characteristics
1074
Clock Timing
1075
Control Signal Timing
1077
Bus Timing
1079
DMAC Timing
1088
Timing of On-Chip Supporting Modules
1092
A/D Conversion Characteristics
1100
D/A Conversion Characteristics
1101
Flash Memory Characteristics
1102
Usage Note
1103
Section 26 Electrical Characteristics (H8S/2633R)
1105
Absolute Maximum Ratings
1105
DC Characteristics
1106
AC Characteristics
1111
Clock Timing
1112
Control Signal Timing
1114
Bus Timing
1116
DMAC Timing
1125
Timing of On-Chip Supporting Modules
1129
A/D Conversion Characteristics
1136
D/A Conversion Characteristics
1137
Flash Memory Characteristics
1138
Usage Note
1139
Section 27 Electrical Characteristics (H8S/2695)
1141
Absolute Maximum Ratings
1141
DC Characteristics
1142
AC Characteristics
1145
Clock Timing
1146
Control Signal Timing
1148
Bus Timing
1150
Timing of On-Chip Supporting Modules
1157
A/D Conversion Characteristics
1160
Usage Note
1160
Appendix A Instruction Set
1161
Instruction List
1161
Instruction Codes
1185
Operation Code Map
1200
Number of States Required for Instruction Execution
1204
Bus States During Instruction Execution
1218
Condition Code Modification
1232
Appendix B Internal I/O Register
1238
B.1A Addresses (H8S/2633 Series, H8S/2633F, H8S/2633R)
1238
B.1B Addresses (H8S/2695)
1248
Functions
1255
Appendix C I/O Port Block Diagrams
1353
Port 1 Block Diagram
1353
Port 3 Block Diagram
1359
Port 4 Block Diagram
1367
Port 7 Block Diagram
1368
Port 9 Block Diagram
1375
Port a Block Diagram
1376
Port B Block Diagram
1380
Port C Block Diagram
1381
Port D Block Diagram
1383
Port E Block Diagram
1384
Port F Block Diagram
1385
Port G Block Diagram
1393
Port 1 Block Diagram
1397
Port 3 Block Diagram
1403
Port 4 Block Diagram
1411
Port 7 Block Diagram
1412
Port 9 Block Diagram
1419
Port a Block Diagram
1420

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