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10B.12.2 Register Configuration
Table 10B-20 shows the port F register configuration.
Table 10B-20 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Notes: *1 Lower 16 bits of the address.
*2 Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit
:
7
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6
Initial value :
1
R/W
:
W
Mode 7
Initial value :
0
R/W
:
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 4 to
6, and to H'00 in mode 7. It retains its prior state by a manual reset or in software standby mode.
The OPE bit in SBYCR is used to select whether the bus control output pins retain their output
state or become high-impedance when a transition is made to software standby mode.
• Modes 4 to 6
Pin PF7 functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BREQO, BACK, and
BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes
the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input
port.
502
Abbreviation
PFDDR
PFDR
PORTF
6
5
4
0
0
0
W
W
W
0
0
0
W
W
W
R/W
Initial Value
2
H'80/H'00 *
W
R/W
H'00
R
Undefined
3
2
0
0
W
W
0
0
W
W
Address *
1
H'FE3E
H'FF0E
H'FFBE
1
0
0
0
W
W
0
0
W
W
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