Renesas H8S/2633 Series Hardware Manual page 233

Bit 4—OE Select (OES): Selects the CS3 pin as the OE pin.
Bit 4
OES Description
Uses the CS3 pin as the port or as CS3 signal output
0
1 When only area 2 is set for DRAM, or when areas 2 to 5 are set as
contiguous DRAM space, the CS3 pin is used as the OE pin
Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the
DMAC single address transfer bus timing.
Bit 3
DDS Description
0 When performing DMAC single address transfers to DRAM, always execute full
access. The DACK signal is output as a low-level signal from the T
1 Burst access is also possible when performing DMAC single address
tranfers to DRAM. The DACK signal is output as a low-level signal
from the T
Bit 2—Read CAS Timing Select (RCTS): Selects the CAS signal output timing.
Bit 2
RCTS Description
CAS signal output timing is same when reading and writing
0
When reading, CAS signal is asserted half cycle earlier than when writing
1
Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write
buffer function in the external write cycle or the DMAC* single address cycle.
Bit 1
WDBE Description
0 Write data buffer function not used
1 Write data buffer function used
or T cycle
C1 2
(Initial value)
or T cycle
r 1
(Initial value)
(Initial value)
(Initial value)
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