Renesas H8S/2633 Series Hardware Manual page 367

Figure 8-30 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
ø
Address bus
HWR
LWR
DACK
TEND
Bus
release
Figure 8-30 Example of Single Address Mode (Word Write) Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
DMA write
Bus
release
DMA write
Bus
release
DMA
DMA write dead
Last transfer Bus
cycle release
313