Renesas H8S/2633 Series Hardware Manual page 649

Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 11-51 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
TCNT
TGR
Figure 11-51 Contention between TGR Write and Compare Match
TGR write cycle
T1 T2
TGR address
N N+1
N M
TGR write data
Inhibited
595