Renesas H8S/2633 Series Hardware Manual page 266

(2) Insertion of Pin Waits
When the WAITE bit of BCRH is set to 1, wait input via the WAIT pin is valid regardless of the
ASTCR AST bit. In this state, a program wait is inserted when the DRAM space is accessed. If the
WAIT pin level is Low at the fall in ø in the final T
level of the WAIT pin is kept Low, T
When wait states are inserted via the WAIT pin, the CAS when writing is output after the T
Figure 7-18 shows example timing for the insertion of wait states via the WAIT pin.
Address bus
AS
CSn (RAS)
CAS, LCAS
Read
RD
Data bus
CAS, LCAS
Write
HWR (WE)
Data bus
Note: ↓ shows timing for /WAIT pin sampling.
n= 2 to 5
Figure 7-18 Example Timing for Insertion of Wait States via WAIT Pin
212
is inserted until the level of the WAIT pin changes to High.
w
T
p
ø
or T state, a further T
c1 w
Program
waits
T T T
r c1 w
RCTS= 0
RCTS= 1
is inserted. If the
w
WAIT pin wait states
T T
w c2
Read data
Write data
state.
w