Renesas H8S/2633 Series Hardware Manual page 732

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WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified.

WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal

reset request and an NMI request when the TCNT overflows during the watchdog timer mode.

NMI request.

Internal reset request.

Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock

sources, obtained by dividing the system clock (ø) or subclock (ø SUB), for input to TCNT.

Note: In the case of the H8S/2695, only 0 should be written to the RST/NMI bit in the TCSR1

WDT0 Input Clock Select

Note: * An overflow period is the time interval between the start of counting up from H'00 on the

TCNT and the occurrence of a TCNT overflow.

Overflow Period* (where ø = 25 MHz)

ø/2 (Initial value)

(Initial value)