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10B.5.2 Register Configuration
Table 10B-7 shows the port 7 register configuration.
Table 10B-7 Port 7 Register Configuration
Name
Port 7 data direction register
Port 7 data register
Port 7 register
Note: * Lower 16 bits of the address.
Port 7 Data Direction Register (P7DDR)
Bit
:
7
P77DDR
Initial value :
0
R/W
:
W
P7DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 7 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P7DDR to 1, the corresponding port 7 pins become output, and by clearing to 0 they
become input.
P7DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. SCI is initialized by a manual
reset, so the pin state is determined by the specification of P7DDR and P7DR.
466
Abbreviation
P7DDR
P7DR
PORT7
6
5
P76DDR
P75DDR
P74DDR
0
0
W
W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
4
3
2
P73DDR
P72DDR
0
0
0
W
W
W
Address*
H'FE36
H'FF06
H'FFB6
1
0
P71DDR
P70DDR
0
0
W
W
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