Renesas H8S/2633 Series Hardware Manual page 651

Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 11-53 shows the timing in this case.
ø
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Figure 11-53 Contention between TGR Read and Input Capture
TGR read cycle
T1 T2
TGR address
X M
M
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